1. Field of Use
This invention relates generally to data processing systems and more particularly to error detection and correction apparatus included within the memory of a data processing system.
2. Prior Art
It is well known to utilize metal oxide semiconductor field effect transistor (MOSFET) memory elements in main memory systems. Since such memories are volatile in nature and require continual restoration of the stored information, error detection and correction apparatus are normally included within such memory systems for ensuring the integrity of the stored information. Generally, main storage systems utilize a modified Hamming code for single error correction/double error detection. Normally, such codes increase significantly the number of memory circuits.
In order to increase memory reliability notwithstanding attendant increases in error detection and correction circuits, at least one system utilizes codes which improve upon the modified Hamming SEC/DED codes and simplify the memory circuit implementation as well as provide faster and better error detection capability. This arrangement is described in a paper "A Class of Optimal Minimum Odd-Weight-Column SEC/DED Codes" by M. Y. Hsiao which appears in the publication "IBM Journal of Research and Development", July, 1970. The construction of such codes is described in terms of a parity check matrix H. The selection of the columns of the H matrix for a given (n, k) code is based upon the following constraints:
1. Every column should have an odd number one's; PA1 2. The total number of one's in the H matrix should be a minimum; and, PA1 3. The number of one's in each row of the H matrix should be made equal or as close as possible to the average number.
Errors are indicated by analyzing the syndromes formed from the data and coded check bits. An odd number of syndrome bits indicates a single error while an even number of syndrome bits indicate a double or uncorrectable error.
The above arrangement was found unsuitable for use in data processing systems where data bytes are transferred by a plurality of devices along a common bus at a rapid rate. The reason was that by the time the parity encoded data word could be checked, the data device applying the data will have relinquished its control of the bus. Hence, requiring the sending device to be connected to the bus until checking was complete results in a reduction in system throughput.
In order to overcome this disadvantage, the apparatus disclosed in U.S. Pat. No. 4,072,853 was included in a memory subsystem so as to force selectively the check code bits written into memory to predetermined states when the parity bits of unchecked data received from a device indicated that the data is in error. This enabled the apparatus to signal that the data was in error when it was originally written into memory upon being read out during a subsequent read cycle of operation.
It was found that there were instances when a bus parity error could go undetected. This occurred when there was a single bit error in an addressed memory location which combined with the bus parity error to modify the coded check bits so as to cause the bus parity condition to go undetected. While this was not a major problem in the past system, the higher frequency of soft error occurrences due in part to alpha particle contamination in MOSFET memories was found to render the error detection capability of such memory systems less reliable. For a more detailed discussion of soft errors, reference may be made to the copending patent application of Robert B. Johnson and Chester M. Nibby, Jr., titled "Soft Error Rewrite Control System", Ser. No. 172,485, filed on July 25, 1980. Also, the system was unable to detect multibyte signals.
In addition to the above, the system disclosed in U.S. Pat. No. 3,836,957 provides for detection of single bus byte parity errors by modifying the generated check code bits to enable recreation of a bus byte parity error for subsequent detection. Also, IBM Technical Disclosure Bulletin titled "Implied Retention of Byte Parity Bits When Using Error Correcting Codes" by R. J. Stanton, et al., published in Vol. 10, No. 7, dated December 1967 discloses apparatus which modifies the generated check bits which also enables recreation of a bus byte parity error.
It was noted that in the system disclosed in U.S. Pat. No. 3,836,957, the occurrence of bus parity errors in more than one byte is detected as a multiple error which causes a halt in systems operations. This has the same disadvantage of reducing memory throughput as discussed above. As concerns the system of the IBM Disclosure Bulletin, the occurrence of a bus byte parity error can go undetected in systems subject to soft error conditions.
Accordingly, it is a primary object of the present invention to provide an improved apparatus for deferring the detection and correction errors within the parity encoded data bytes received from any one of a plurality of input/output devices for storage in a memory subsystem.
It is another object of the present invention to provide improved apparatus for use in a memory subsystem susceptible to soft errors which connect to high speed common bus system.
It is still a further object of the present invention to provide an arrangement for detecting and correcting errors in a manner which requires a minimum of additional circuits.